The present invention relates to timing measurements, and more particularly to transport delay and jitter measurements in clock driven systems.
In clock driven systems a reference clock propagates through different paths, with the layouts of the paths introducing different delays for the reference clock. Certain circuits along the paths, such as clock data recovery (CDR) circuits, introduce additional delays. High speed chipsets used for transmitting data at multiple gigabits per second present numerous signal integrity challenges. Although a high speed backplane may seem like just a printed circuit (PC) board, it really may be viewed as a communications system. The reference clock that propagates to different parts of the backplane experiences different transport delays. System designs need to take into account the transport delays to make system performance meet requirements, such as limits to jitter.
For high speed serial data standards, such as the Peripheral Component Interface (PCI) Express and Fully Buffered Dual In-line Memory Module (FB-DIMM) standards, the physical layer may be described as shown in FIG. 1. The reference or system clock drives both a transmitter (TX) and receiver (RX) through phase locked loops (PLL) in each. The PLLs have transport delays that may be viewed as jitter transfer delays. In general the PLL characteristic has jitter transfer delay as a function of frequency. In the working frequency range a group delay is used to represent transfer delay. The transport delay of the PLL may be measured by spectrum analyzers. Transmission lines, including microstrips and striplines, also have transport delays that may be measured using Time Domain Transmissometry (TDT) or Vector Network Analyzer (VNA). For the system shown in FIG. 1 the overall transport delay is obtained by summing up the transport delays of each component, such as the PLLs and transmission lines, if the transport delay of each component is provided by component vendors. However it is very difficult, if not impossible, to use the currently available techniques (spectrum analysis, TDT, VNA) to measure directly the transport delays.
What is desired is a direct method for measuring transport delays and jitter on a high speed printed circuit board.